1. Field of the Invention
This invention relates to a test assistant system for a logic design process, which is capable of automatically executing a test pattern generating operation and a functional simulation required for a logic design of a logic circuit system.
2. Description of the Prior Art
A test pattern generating operation for generating test patterns must be required to evaluate logic circuits designed by a designer.
There is a method to design a logic circuit, by which existing logic gates which are stored in a gate cell library are combined to generate the logic circuit. There are two methods used for a combinational circuit and for a sequential circuit, for a test pattern generating method for the logic circuit designed by using the method.
There are the D-algorithm, the ENF method, Poage's method, the boolean differential method, the random testing generating method, and the PODEM method as test input generating methods used for the combinational circuit.
In addition, there are Poage's method, the random testing method, and the compact testing method as test generation methods used for the sequential circuit.
In these test pattern generating methods used for the logic gates such as the combinational circuit and the sequential circuit, test patterns for all events are generated by the methods at the same time since testing data cannot be distinguished from a control signal.
Accordingly, an enormous number of test patterns are generated for a large integrated circuit, for example, including more than 50K gates, by the test pattern generating methods described above.
Namely, these test pattern generating methods should be used for the logic circuits including less than 10 k gates.
On the other hand, there are design methods which use a hardware descriptional language (HDL) of the register transfer (RT) level to describe various logical functions. The logical gates are interconnected by using descriptions (statements) in the hardware descriptional language.
Test patterns for testing the logical functions of a logical circuit obtained by using the method are provided from a functional design data base comprising the descriptions for the logical functions.
The RT-level hardward descriptional language can mainly generate test patterns for data transfers between registers.
The test pattern generating method based on the RT-level language have been reported in the following literature.
T.LIN & S.Y.H.SU, The S-algorithm, "A promising Solution for Systematic Functional Test Generation", IEEE TRANS. on COMPUTER-AIDED DESIGN, VOL. CAD-4. No. 3, July 1985".
The functional design data base for logical design comprises a statement correspondence table in which the statements expressing the logical functions of the logical circuits are included, a circuit component table for expressing logical circuit components of the functions corresponding to the statements, and a dependent relationship table for expressing relationships between the statements.
When test patterns for logical circuits are therefore generated by a generator, the test patterns must be generated in consideration of all information of signals operated in the logical circuits because the kinds of signals handled in the statements cannot be distinguished from one another.
Namely, it takes much time to generate the test patterns in the prior art.
A simulator which uses the test patterns generated by the test pattern generator is also important for the logical design.
There are the level sort method and the event driven method as simulations for a logical system. These are well known in the prior art.
In the level sort method, the level (the level number) of each component in a logical circuit is determined in accordance with the number of steps observed from an input terminal of the logical circuit.
The order of evaluation of each component (for example, an AND gate, an OR, gate and the like as the logical components in the logical circuit) is determined based on the level numbers, then all logical components in the logical circuit are evaluated each time an input vector is provided as a test pattern at one cycle time in the logical circuit.
In general, the level sort method is used by using a compile method in which statements written with a general purpose language or described for the hardware description are translated to sequential machine codes by a compiler. Accordingly, the simulation can be carried out efficiently because control of events that mean changes of signals is not necessary in the level sort method.
However, since it is difficult for the level sort method to handle on asynchronous circuit, the level sort method can handle only a simple combinational circuit and a synchronous circuit.
On the other hand, in the event driven method, only a component in which input level provided from other components is changed is evaluated while transferring the changed input level.
An asynchronous circuit can be easily handled by the event driven method. Moreover, timing analysis of the component can be treated easily by the event driven method. However, the event driven method takes much time because it is frequently executed by using an interpreter method. An evaluation time and an over head as a control time for a circuit operation in the event driven method takes longer than that of the level sort method.
Moreover, in the event driven method, evaluation of not use is yielded by the differences of the number of the levels from the input terminal to each component in the logic circuit.
A simulator based on the event driven method in the prior art is described with reference to FIGS. 1 to 3.
The simulator 130 comprises a functional design data base 131, an event buffer 132, an event evaluation portion 133, and an event registration portion 134.
FIG. 2 is an example of the hardware description for a logical component. In the same diagram, the hardware description 140 describes input terminals A, B, C, and D, output terminal Z, internal signals S1, S2, and S3, and statements 141 (S1=A and B), 142 (S2=S1 and C), 143 (S3=S2 and D), and 144(Z=S3).
There are a data transfer statement, a condition statement and the like as kinds of statements in the hardware description.
As shown in FIG. 3, when the high level ("1") is provided to the input terminals A, B, and D and the low level ("0") is provided to the input terminal C, then the low level is provided to the terminal A and the high level is supplied to the terminal C as a test pattern at the timing T1 so that the events of the terminals A and C are generated. The event information of the terminals A and C is stored in the event buffer 132.
In the event evaluation portion 133, this event information from the terminals A and C is read out to evaluate the statements 141 and 142. In this case, as the events occur in the internal signals S1 and S2, they are stored in the event buffer 132 by the event registration portion 134.
Next, the statements 142 and 143 are evaluated by using the events of the internal signals S1 and S2 and which are stored in the event buffer 132, then the events of the internal signals S2 and S3 are stored in the event buffer 132 by the event registration portion 134.
Similarly, the statements 143 and 144 are evaluated by the events of the signals S2 and S3, then the events of the internal signal S3 and the output terminal Z are registered in the event buffer 132.
Finally, the statement 144 is evaluated by the event of the signal S3 to register the event of the output terminal Z.
Then, when there is no statement evaluated by the event of output terminal Z, the simulation for one vector at the timing T1 is completed.
As clearly described above, the simulator 130 evaluates these statements of 142 to 144 twice.
To summarize the problems in the prior art, a great number of the data paths (chains) are generated for an actual complicated logical circuit in the conventional test pattern generating method of the register transfer (RT) level.
Accordingly, it is possible to use the conventional test pattern genarating methods only for a simple logical circuit other than complicated large integrated logical circuits.
In addition, it is impossible for the simulator based on the level sort method to handle an asynchronous circuit, evaluation of not use occurs in the event driven method.